Information transfer between magnetizable wires



Dec. 30, 1969 woo F. CHOW 3,487,382

INFORMATION TRANSFER BETWEEN MAGNETIZABLE WIRES Filed Feb. 7 1966 3 Sheets-Sheet 1.

CD 2 fi r l (9 'u.

b vsuroe woo F. CHOW ATTORNEY Dec. 30, 1969 woo F. c ow 3,487,382

INFORMATION TRANSFER BETWEEN MAGNETIZABLE WIRES Filed Feb. 7, 1966 3 Sheets-Sheet l FIG. 3

United States Patent O 3,487,382 INFORMATION TRANSFER BETWEEN MAGNETIZABLE WIRES Woo F. Chow, 910 Jenifer Road, Horsham, Pa. 19044 Filed Feb. 7, 1966, Ser. No. 525,652 Int. Cl. G11b /00 US. Cl. 340-174 16 Claims ABSTRACT OF THE DISCLOSURE There is disclosed an invention for transmitting data from a first to a second plated wire of a certain length via a third plated Wire which has a shorter length and therefore a lower impedance.

This invention relates to a technique which can transfer information stored along one magnetizable wire to a second magnetizable wire without the need for external amplifying devices.

In the present state of the art, it is diflicult to transmit information from one location to another location along a relatively long magnetizable wire without the aid of an external amplifying device since the impedance of the wire increases with length and hence, insufficient current is generated in the wire to accomplish the technique of bit steering. This is a recognized limitation whenever information must be transferred over a relatively long distance.

Accordingly, the following are deemed objects of the present invention: to provide a new and improved information transfer technique; to provide a new and improved information transfer technique using magnetizable wires; to provide a new and improved information transfer technique which requires no external amplifying circuitry; to provide a new and improved technique for transferring information along a relatively long magnetizable wire. Other objects of this invention will become apparent to those of ordinary skill in the art by reference to the following detailed description of the apparatus and the appended claims. The various features of the invention may be best understood with reference to the accompanying drawings wherein FIGURE 1 shows the overall arrangement of the information transfer technique and FIGURES 2 and 3 show the logical implementation and the timing diagram for FIGURE 1.

Referring now to FIGURE 1, there is depicted the information transfer apparatus which is formed essentially of a plurality of horizontally oriented magnetizable wires 1-6 (hereinafter referred to as plated wires). Conventionally, the plated wires 1-6 are five mil berrylium-copper substrates, upon whose surface is plated a thin, magnetic film. The magnetic film is electroplated on the wire surface with approximately a 10,000 Angstrom thickness of Permalloy (iron-nickel alloy). The Permalloy coating is electroplated in the presence of a circumferential magnetic field that establishes a uniaxial anisotropy axis at right angles (i.e., around the circumference) to the length of the wire. The uniaxial anisotropy establishes an easy and hard direction of magnetization and the magnetization vectors of the thin film are normally oriented in a first or second equilibrium pisition along the easy axis, (i.e., a preferred axis), thereby establishing two bistable states neceesary for binary logic applications.

Positioned in juxtaposition and substantially orthogonal to the plated wires 1-6 are a plurality of conductors -13 and 14-17. The conductors are typically -50 mils in Width and are formed on an insulating substrate (not shown) such as Mylar. The conductors 10-13 and 14-17 are divided into two groups (Send A and Send B) for reasons which will be discussed hereinafter. One end of Ice the conductors is grounded and the remaining ends are connected to the driver circuits 24 and 25, respectively. The conductors 12 and 16 are reference conductors and the locations 37, 37 and 48, for example, are permanently magnetized as ls similarly the conductors 13 and 17 are reference complement conductors and the locations 38, 38' and 50 are permanently magnetized as Os. The reason for this will become apparent hereinafter.

Oriented on the left-hand side of FIGURE 1 are the short plated wires 7, 8, and 9. These short plated wires 7, 8 and 9 are of the same physical characteristics as those previously described with regard to plated wires 1-6. One short wire, for example wire 7, is connected to two long plated wires 1 and 2 by means of the copper pad 20. The pads 18 to 20 are merely low impedance connectors and, by way of example, may comprise a printed circuit connection. In like manner, short plated wires 10, 11 and 12 are oriented on the right-hand side of the drawing between pairs of plated wires. However, it should be noted, for example, that the short plated wire 10 is connected to the long plated wires 2 and 3 by means of the copper pad 22. Both the long wires and the short wires are mechanically embedded in a plane such, for example, as disclosed in the co-pending application of Woo F.- Chow, Ser. No. 499,971, filed Oct. 21, 1965, which pro vides a low impedance return path for each combination of a long and two short Wires. The plane which provides the low impedance return path is not shown in order to keep the drawing as simple as possible. It should be noted that a small section 27, 28 and 29, for example, of each long plated wire 1-6 under the Send A or Send B conductors is of smaller diameter than is the main body thereof. This smaller diameter represents a portion of plated wire which does not have plating and hence, cannot be magnetized.

The various data bits (that is the binary Os or 1s) are stored along the length of the plated wires 1-6 between Send A and Send B conductors. It should be noted, however, this embodiment does not exclude the possibility of data storage in the leftand the right-hand side plated wires such as 7, 8, 9 and 10, 11, 12. Binary information, for example, is stored at the intersections formed conductors 30 and 31 with respective to plated wires 1-6. By way of example, a binary 1 data bit may be stored at the location 32 and its complement or binary 0 may be stored at the location 33. The complement bit, it should be understood, is not essential to the operation of the instant invention but may be required to be transferred for certain applications and therefore will be discussed below. Only two straps 30 and 31 are shown in order to keep the discussion which follows as simple as possible. The binary 1 data bit at location 32 will be represented by a clockwise orientation as viewed from the right-hand side of the plated wires 1-6 and the binary 0 complement bit at the location 33 will have a counterclockwise orientation around the circumference.

Let us assume that it is required to transfer the information along plated wire 1 to plated wire 2 and then to plated wire 3 in an upward direction. In operation, the binary 1 data bit at location 32 is transferred to the locations 34 and the complement bit at location 33 is transferred to locations 35 by the technique of bit-current steering which is fully described in the co-pending application of Woo F. Chow, Ser. No. 466,904, filed June 25, 1965. This is accomplished in the following manner. The conductor 10 is energized by the driver and selection circuit 24 with a signal pulse thereby causing current to flow in an upward direction toward ground. The energizing of conductor 10 causes the magnetization vectors at the bit locations 34 to be rotated to an angle less than degrees from the preferred axis of magnetization. While the vectors are thus oriented (i.e., biased), the conductor 30 is energized by the driver circuit 36 thereby rotating the magnetization vectors at the location 32 which are magnetized as a I to an angle less than 90 degrees. This rotation induces a voltage in the plated wire 1. This induced voltage produces a current 11 in plated wire in accordance with Lenzs law which causes the magnetization vectors at the location 34 to become magnetized as a 1. In like manner, the complement bit at the location 33 is transferred to the bit location 35. This may be accomplished in one of several ways. One such Way is in precisely the same manner as was just described. Thus, conductor 11 is energized by the driver and selection circuit 24 thereby biasing the magnetization vectors at location 35. While the vectors are thus oriented, conductor 31 is energized thereby causing the magnetization vectors at location 33 to be rotated. This induces a voltage in plated wire 1 and causes the steering current I1 to flow and so magnetize the vectors at locations 35 as a 0. Another way to record the complement is to bias the vectors at location 35 at a period of time so that the fall time of steering current occurs just before the fall time of the bias signal applied to conductor 11. In summary therefore, the first step in the transfer of information from a first plated wire to a second plated wire involves transferring the information bit and its complement to the locations 34 and 35, respectively. In other words, the data and its complement are momentarily stored along the Send A conductors and 11.

The 1 data bit which is now stored in the bit location 34 is next transferred to the bit location 41 which is located along the short plated wire section 7. This is accomplished in the following manner. The conductor 39 is energized by means of the driver and selection circuit 23. The location 41 is thereby conditioned so that information can be transferred to these locations by the technique of bit steering. Thus, by energizing strap 39 the magnetization vectors at the location 41 are biased to the slightly less than 90 degree position. While the magnetization vectors are so oriented, the conductors 10 (the data conductor) is energized by means of the driver selection circuit 24. The energizing of conductor 10 causes a voltage to be induced in plated wire 1. No voltage is induced in plated wire 2 since there is no magnetic material along this portion of the wire as previously mentioned. Since, the location 34 is magnetized as a binary 1 (i.e., in the clockwise direction), the induced voltage causes a steering current to flow in plated wire 1 in the direction of I1. The steering current flows in the direction of I1 to oppose the reduction of flux in the clockwise direction caused by the rotation of the magnetization vectors at the location 34. The steering current which is generated in the plated wire 1 can complete a circuit either through the copper pad and the short plate wire section 7 to ground or through the copper pad 20 through the plated wire 2, the copper pad 22 and short plated wire section 10 to ground. However, most of the steering current completes the circuit through the short plated wire section 7 rather than through the circuit through the long plated wire 2 since the former provides a much lower impedance path. In other words, the physical dimensions of the plated wire 7 and 2 control which has the greater or lesser impedance. In the event that the physical length of the long and the short plated wires mentioned above are close, resistance and/or inductance can be inserted to make the long plated wires 16 electrical long. Consequently, the data bit (i.e., the binary 1) which was located at the position 32 and which was transferred to the location 34 is now transferred to the location 41 by means of the technique of bit steering. The complement bit may also be transferred to location 42 by direct transfer from location or by utilizing the fall time of the steering current developed to record the 1 at location 41.

The 1 data bit which is located at the bit position 41 along plated wire 7 is next transferred to the location 43 along plated wire 2 in the following manner. The conductor 30 is energized by the driver 36 and the magnetization vectors at the location 43 are biased or rotated to an angle less than degrees from the preferred axis of magnetization. The conductors 39 and 11 are then simultaneously energized, respectively, by the driver and selection circuits 23 and 24. The current I2 is caused to fiow in plated wire section 7, the current 14 in plated wire 2 and the current I3 in plated wire 1. It should be noted that the current 14 in plated wire 2 is not caused by an induced voltage therein but it forms a resistive load for the currents flowing in plated wires 7 and 1 as will be explained in greater detail hereinafter. The steering current I4 is approximately equal to the current I2 as will be shown hereinafter and is of a magnitude to steer the magnetization vectors at the location 43 to a binary 1 or clockwise orientation and the current 13 is therefore practical zero. The 0 complement bit is transferred by energizing conductors 40 and 10 simultaneously after conductor 31 has been energized and the magnetizing vectors at location 44 have been biased. A steering current is thereby developed in plated wires 2 and 7 which flows from left to right and the vectors at location 44 become magnetized as a 0. Substantially no current flows in plated wire 1 as was described above. The complement bit may also be recorded at location 44 when the drive strap 31 is energized by the driver circuit 36 with a signal that occurs at a slightly later time than does the energizing signal applied to the strap 30. By this expedient the steering current pulse (I4) is made to occur slightly before the fall time of the energizing signal applied to conductor 30 to record the data bit (a l) whereas the steering current pulse produced by the fall time of the energizing signal of 39 is made to occur slightly before the fall time of the energizing signal applied to conductor 31 to record the complement bit (a 0). The transfer of the complement bit will be explained in greater detail hereinafter in conjunction with the logical arrangement of FIGURE 2 and the timing diagram of FIGURE 3.

As was briefly mentioned above in transferring the 1 data 'bit the current 13 in plated wire 1 is of relatively small magnitude so that the steering current 14 in plated wire 2 approximately equals the current I2 in plated wire 7. This may be demonstrated as follows. An equivalent circuit may be formed which consists of three parallel branches. The first branch of the parallel circuit comprises the voltage generator which represents the voltage (V1) induced in plated wire section 7 by the rotation of the magnetization vectors at the bit location 41 as well as the equivalent resistance (R1) of the plated wire 7. The second branch of the equivalent circuit comprises the voltage generator which represents the second voltage (of the same polarity and magnitude as the first) and is produced by the rotation of the magnetization vectors at the location 35. In series with the last mentioned voltage is a resistance (R2) which is larger than the resistance (R1) of the first parallel branch because plated wire 1 is physically and/or electrically longer than plated wire 7. The third branch of the parallel equivalent circuit comprises the resistance of the plated wire 2 (i.e., the load resistance) which is of the same magnitude as the resistance in the second branch of the equivalent parallel circuit because plated wires 1 and 2 have the same length dimensions. By observing the operation of the three branch parallel equivalent circuit, it can be readily seen that the load current I4=I2+I3. In other words, since the third branch contains the load, the first and second branches containing the voltage generators provided all the current for the load. However, the equivalent voltage across the two branches containing the voltage generators is equal to the following:

wherein I2 represents the current through the short plated wire 7 and 13 represents the current through the long plated wire 1. Since V1 on both sides of the equation are equal (i.e., the induced voltages are equal) they may be cancelled and hence,

It can therefore be appreciated that since R2 (i.e., the resistance of plated wire 1) is much greater than the resistance R1 (the resistance of the short plated wire section 7) I3 is only a fractional portion of I2. For this reason, 14 approximately equals I2 and therefore substantially all the steering current is considered to flow in plated wires 2 and 7. Hence, the current I4 is of sufficient magnitude to steer the magnetization vectors at the bit location 43 to a 1 orientation. Furthermore, since little current is developed in plated wire 1, the information will not be changed in location 32. Therefore, the information stored at the location 32 along plated wire 1 has been transferred to location 43 along plated wire 2. It is therefore apparent from the above discussion that data in the odd numbered long plated wire such as 1 can be temporarily stored in the send conductor group A and can be transferred upward via the left-hand short plated wire 7. Data can also be transferred from an odd numbered plated wire in a downward direction via the righthand side short plated Wires via the send straps A in the following manner.

Assume that the 1 data bit located along the odd numbered plate Wire 3 at the location 45 is to be transferred in a downward direction to the location 43 along palted Wire 2. The 1 data bit and the 0 complement bit are first transferred to the locations 34' and 35, respectively. The 1 data bit at location 45 is transferred to location 34' in the following manner. The conductor is energized by means of the driver and selection circuit 24 so that the magnetization vectors at location 34 'are biased. The conductor 30 is then energized by means of the driver circuit 36. A voltage is thereby induced in plated wire 3 which causes the steering current 18 to flow therein. By means of the steering current 18, the magnetization vectors at the bit location 34 are magnetized in a clockwise direction as a binary l." In like manner, the complement 0 bit at location 55 is transferred to the locations 35'. Thus, the conductor 11 is energized by the driver and selection circuit 24. This causes the magnetization vectors at locations 35 to be biased. While the vectors are thus oriented, the conductor 31 is energized thereby inducting a voltage in plated wire 3. This voltage causes a current to flow in the direction of 16. The steering current I6 thereby causes the magnetization vectors at location 35' to be switched to the counterclockwise direction. It will be recalled that the complement bit may be transferred to location 35 by having the fall time of the steering pulse occur slightly ahead of the fall time of the energizing signal applied to conductor 11. The information at location 34' is next transferred to the location 41 along the short plated wire section 10. Conductors 10 is energized by the driver and selection circuit 24 slightly after the conductor 39' is energized by means of the driver circuit 26. This causes the information stored at the location 41 to become magnetized in the clockwise direction as binary ls by the technique of bit steering. The 0 complement bit is transferred to location 42' by either of the two techniques described above, namely, by transferring the 0 bit from locations 35 to location 42' directly or by using the fall time of the steering pulse developed by transferring the 1 bit. The 1 information bit is next transferred to the bit location 43 along the plated wire 2 by simultaneously energizing the conductor 11 simultaneously with the energizing of the conductor 39 by means of the driver circuits 24, 26, respectively. The energizing of the conductor 11 and 39' causes the steering current I7 and I5 to be developed in plated wires 2 and 10 where in 17 approximately equals I5. Hence the magnetization vectors at the location 43 are magnetized in a clockwise direction or as a binary 1. Therefore, the binary l which was stored at location 45 has been moved in a downward direction and is transferred to the location 43 along plated wire 2. The complement 0 bit at location 55 may be also transferred to location 44 in the manner previously described. Thus, the 0 complement bit is first transferred to location 35' and then to location 42'. The complement is next transferred to location 44 by simultaneously energizing conductors 40 and 10 thereby developing steering current in plated wire 2 to magnetize the vectors at location 44 to the 0 direction. Information may be therefore transferred in the odd numbered plated wires such as 1 and 3 in an upward direction by temporarily storing the data along the send conductors A and the short plated wires 7, 8 or 9 and information may be transferred in a downward direction by temporarily storing the data along the send conductors A and the short plated wires 10, 11 or 12.

In a similar manner the data stored along the even numbered plated wires are stored temporarily in the send conductors B and can be transferred in an upward or downward direction. The upward transfer will be briefly summarized as follows. The information at location 46 (a 0) along the even numbered plated wire 4 is transferred along its length to the bit position 47 and the complement (a 1) stored at location 56 is transferred to the location 49 (i.e., the data and its complement are temporarily stored along the send B conductors). The data and complement bit at locations 47 and 49 are next transferred to locations 51 and 52, respectively, by the technique of bit steering. Conductors 15 and 39' are then simultaneously energized shortly after conductor 30 is energized (i.e., in order to bias location 53) and the vectors thereat become magnetized as a 0. The complement bit is transferred to location 57 by energizing the conductor 31 via the driver and selection circuit 36 to bias location 57 shortly after location 53 has been biased. The fall time of the steering current pulse required to write a 0 in location 53 is then utilized to write a 1 in location 57. A 1 may also be transferred to location 57 by simultaneously energizing conductors 14 and 40' so that a steering current is developed in plated wire 5. By properly biasing location 57 before the steering current is developed, location 57 becomes magnetized as a 1. Hence, the 0 information bit at location 46 has been transferred in an upward direction to location 53 along plated wire 5 via the short plated wire conductor 11 and the send B conductors. Information along the even numbered plated wire 4 is transferred in a downward direction in the following manner. The information (i.e., a O) at location 46 is first transferred to the location 47 and its complement (i.e., a l) at location 56 is transferred to the location 49. The 0 data bit at location 47 is next transferred to location 53 and the 1 complement bit is transferred to location 54. Conductor 30 is then energized in order to bias the vectors at location 45. Conductors 39 and 15 are next simultaneously energized to develope a steering current in plated wire 3. The 0 bit location 46 is therefore transferred to location 45. The complement or 1 bit can also be transferred to location 55 in accordance with one of the techniques above described. It is therefore apparent that information can also be transferred from the even numbered plated wires in a downward direction via sending strap B and plated wire 8.

The subject invention permits the transfer of information to a magnetizable wire several spaces above or below the wire which is storing the data. Thus, the 1 data bit at location 32 and its complement bit stored at location 33 along plated wire 1 can be transferred to the locations 45 and 55, respectivley along plated wire 3 7 without being first recorded along plated wire 2. This is accomplished by transferring the 1 data bit at location 32 to location 34 and the complement bit at location 33 to location by the technique of bit steering. The information and its complement are next transferred to locations 41 and 42 in the manner previously described.

The 1 data bit at location 41 and the O complement bit at location 42 are then transferred respectively to 10- cations 41' and 42. Summarizing this operation, the magnetization vectors at location 41' are first biased by energizing conductor 39'. Conductor 39 is then energized by means of the driver circuit 23 simultaneously with the energizing of conductor 11 by means of the driver and selection circuit 24. This causes a steering pulse to be developed in plated wires 10, 2 and 7 which flows in a direction from right to left. The rise time of the steering pulse occurs slightly after the biasing signal applied to conductor 39'. This causes the location 41' to become magnetized as a 1. The complement bit is also transferred to location 31 by means of the bit steering technique. This is accomplished by energizing conductor 17 shortly after conductor 39 is energized in order to bias the vectors at location 31. By this expedient, the steering current pulse occurs just prior to the fall of the biasing signal so that location 31 is magnetized as a 0. In like manner, the magnetization vectors at the location 42' are magnetized in a counterclockwise direction by a bit steering current which is generated by the simultaneous energizing of conductor by means of the driver circuit 23 and conductors 10 by means of the driver and selection circuit 24. Consequently, a steering current pulse is generated which flows in a left to right direction through plated wires 7, 2 and 10. Before this steering current is generated, the magnetization vectors at location 42 are biased to the less than ninety degree position. The steering current pulse occurs just before the fall time of the biasing pulse so that location 42' is magnetized as a O.

The 1 at location 41 and the 0 at location 42' are next transferred to locations and 55, respectively. Thus, the location 45 is first biased by energizing the conductor 30, shortly after which location is biased by energizing conductor 31. Thereafter conductor 39 is energized simultaneously with conductor -17. A steering current pulse is developed in plated wire 3 which flows in a direction from right to left. The rise time of the steering current pulse is timed to occur just before the fall of the energizing signal which is applied to conductor 30. Consequently, location 45 becomes magnetized as a 1 and the data bit is transferred from location 32 to 45. Substantially no current flows in plated wire 2 during the above described operation. The 0 complement bit is transferred to location 55 by utilizing the fall of the steering current pulse which is made to occur just before the fall time of the energizing signal applied to conductor 31. It is therefore apparent from the above description that information may be transferred to a magnetizable wire several spaces above the wire which is storing the data. Similarly, the data may be transferred several spaces below the wire which is storing the data in the same manner as above described.

In certain situations, it may be desirable or even necessary to utilize the steering current developed by two memory locations which are magnetized in the same direction to write information into a single memory location. Such an arrangement is necessary when the impedance of the plated wire is relatively large, for example, due to its length. The instant invention may be readily adapted to provide the steering power under such circumstances. Accordingly, the Send A and Send B conductors utilize two additional conductors 12, 13, 16 and 17. The conductors 12 and 16 are designated -as reference conductors and the bit position thereunder are permanently magnetized as ls. Furthermore, the conductors 13 and 17 are designated as reference (complement) conductors and are permanently magnetized as Os. In like manner, two

additional conductors are required for the left and right short plated wires. Thus, the reference conductors 30 and 58 are added to the left and right short wires respectively, and the bit locations thereunder are permanently magnetized as ls. Similarly the reference (complement) conductors 32 and 59 are provided and the bit locations along their respective lengths are permanently magnetized as Os.

Before transferring information from, for example, plated wire 1 to plated wire 2, location 41 is reset to a 0 (i.e., the vectors are oriented to the counterclockwise direction) and the location 42 is reset to a 1 (i.e., the vectors are oriented to the clockwise direction). Resetting is accomplished by utilizing the two permanent Os along conductors 13 and 32 and the two permanent ls along conductors 12 and 30. It should be noted that the bit locations along conductors 39 and 40' are similarly reset by utilizing the permanently magnetized locations along conductors 16, 17, 58 and 59.

The data bit at location 32 which is assumed to be a 1, and its complement (0) at location 33 are transferred respectively to locations 34 and 35. This is accomplished by energizing conductor 30 simultaneously with another conductor (not shown) which is continuous only to plated wire 1 and the bit location thereat is permanently magnetized as a 1. As discussed previously, the technique used to transfer a l and a O to locations 34 and 35, respectively, may be a one cycle operation which utilizes the rise and fall time of the steering pulse. The l and the 0 may also be transferred separately, by employing a two cycle operation. It should be noted, however, that in order to transfer or write information in a new location, the steering power generated by the read-out of two locations is utilized. In order words, location 32 and the permanently magnetized l at plated wire 1 along the conductor (not shown) are simultaneously read-out to transfer the 1 data bit to location 34. In the event that the data bit at location 32 is a 0, conductor 30 would be simultaneously energized with another conductor which is contiguous only to plated wire 1 and their intersection is permanently magnetized as a 0. The 1 information bit at location 34 is next transferred to location 41. This is accomplished by simultaneously energizing conductors 10 and 12. A steering current is thereby developed which enables a 1 to be recorded in location 41 after the magnetization vectors at location 41 are properly biased by energizing conductor 39. The complement is recorded in location 42 by utilizing the fall time of the steering current pulse or alternatively, by simultaneously energizing conductors 11 and 13 to develope a 0 steering current. In the event that a 0 data bit was stored in location 34 and complement 1 bit in location 35, the simultaneous energizing of conductors 10 and 12 would produce no steering current since location 34 is magnetized as a 0 and location 37 as a 1. Accordingly, since locations 41 vand 42 were originally reset to a 0 and 1, they will remain magnetized in this direction and the data and its complement will effectively be transferred.

In order to transfer the information to the plated wire 2, conductors 30 and 39 are simultaneously energized with conductors 11 and 13. Since locations 63 and 41 are magnetized as ls and locations 35 and 38 are magnetized as Os, substantially no steering current is developed in plated wire 1. A l is thereby recorded in location 43 and a O in location 44 when the vectors thereat are magnetized. It should be again noted that two bit locations, namely 41 and 63 in conjunction with the two bit locations 35 and 38 (for cancelling purposes in plated wire 1) provide the necessary steering current. If the data bit to be transferred is a 0, then the simultaneous energizing of conductors 30 and 39 with conductors 10 and 12 will produce no steering current in plated wire 2 as well as plated wire 1 so that locations 43 and 44 will remain magnetized as a O and a 1, respectively, (i.e., the reset positions).

From the above description it becomes apparent that the subject invention provides a technique whereby information may be transferred from a first location to a second location by developing a steering current resulting from the read-out of two locations which are magnetized in the same direction. In other words, the read-out of two memory locations provides the steering current power to record in a single location. This is significant when the impedance of the plated wire is high due, for example, to its length.

Referring now to FIGURES 2 and 3 in greater detail, there is depicted the logical arrangement to accomplish the information transfer discussed in FIGURE 1. It should be understood that the logical arrangement to be discussed hereinafter is intended to be exemplary only and that other arrangements might be readily provided. Only the logic to accomplish a transfer from one plated wire to an adjacent plated in an upward or downward direction will be discussed since the logic to accomplish other functions discussed with regard to FIG. 1 might be readily provided by those skilled in the art.

For ease of understanding, a simple one-to-one transfer will be discussed (i.e., the read-out of one location will provide suflicient steering current to record or transfer the information thereat to a second location). The operation of the logic to accomplish a transfer from plated wire 1 to plated wire 2 .(i.e., in an upward direction) is as follows. Assume that a 1 data bit is stored at location 32 and the complement bit is stored in location 33. It will be recalled from the discussion of FIG. 1 that the data bit at location 32 is first transferred to location 34 and the complement bit is transferred to location 35. This is logically accomplished as follows.

The signals T 1-2 (FIG. 30) and TRL (FIG. 3b) are simultaneously applied to the AND gate 64 in order to condition the latter. The conditioning of the AND gate 64 causes a signal to be applied to the OR gate 67 so that the conductor is energized and the vectors at location 34 are biased. The AND gate 79 is then energized by the signals T2-4 (FIG. 3d) and TRL-R (FIG. 3a) so that it becomes conditioned. The conditioning of the AND gate 79 causes an output signal to be applied to the OR gate 77 which in turn causes the condutcor 30 to be energized. Accordingly, by the technique of bit steering, previously described, the 1 information bit at location 32 is transferred to location 34. The complement bit or 0 is transferred to location 35 as follows. The conductor 11 is energized thereby biasing location 35 when the OR gate 68 is conditioned. The OR gate 68 is conditioned by the simultaneous applying of the signals T45 (FIG. 3e) and TRL (FIG. 3b) to the AND gate 63. The output of the AND gate 63 is thereby applied to the OR gate 68 in order to condition the latter. However, the fall time of the steering current pulse (FIG. 3d) which is developed in the plated wire 1 occurs before the fall time of the biasing signal applied to location 35 and hence, the complement or 0 bit is recorded thereat.

The information at location 34 and its complement at location 35 are next transferred, respectively, to locations 41 and 42. This is accomplished by first biasing location 41 by the energizing of conductor 39. This is logically accomplished by applying simultaneously the signals T01 (FIG. 3i) and the signal TRUD (FIG. 3g) to the AND gates 61 in order to condition the latter. The output of the conditioned AND gate 61 is applied to the OR gate 59. Accordingly, conductor 39 is energized at location 41 is biased. The signals T1-3 (FIG. 30) and the Read-Up signal (FIG. 3h) are simultaneously applied to the AND gate 65 in order to condition the latter. The output of the conditioned AND gate 65 is applied to the OR gate '67 and hence, the conductor 10 is energized. Accordingly, the 1 information bit at location 34 is transferred in an upward direction to location 41. The complement bit is transferred from location 35 to 42 ill the following manner. The signals T3-4 (FIG. 3 and TRU-D (FIG. 3g) are simultaneously applied to the AND gate 62 in order to condition the latter. The conditioned AND gate 62 causes the OR gate 60 to be conditioned so that conductor 40 is energized. Therefore, the vectors at location 42 are in the biased condition. Since the steering current pulse developed in plated wires 1 and 7 has a fall time at the end the third clock period (FIG. 30) whereas the fall time of the energizing pulse applied to conductor 40 does not occur until the end of the fourth clock pulse and hence, the complement bit is transferred to location 42.

The information bit is next transferred to location 43 and its complement 'bit to location 44 in the following manner. Location 43 is first biased by energizing conductor 30. This is logically accomplished by applying the signals T56 (FIG. 3d) and TRUD (FIG. 3g) to the AND gate 81. The AND gate 81 is thereby conditioned and an output signal is produced which is applied to the OR gate 77. The OR gate 77 causes conductor 30 to be energized and location 43 to be biased. The conductors 39 and 11 are then simultaneously energized. Conductor 39 is energized by applying the signals T6-8 (FIG. 3i) and TRU-D (FIG. 3g) to the AND gate 61. The AND gate 61 is conditioned which in turn conditions the OR gate '59. Accordingly, conductor 39 is energized. Conductor 11 is logically energized in the following manner. The signals TRU-D (FIG. 3g) and T6-8 (FIG. 3e) are simultaneously applied to the AND gate 66. The AND gate 66 is conditioned thereby conditioning the OR gate 68 so that the conductor 11 is thereby energized. Accordingly, as was previously discussed with respect to FIG. 1, the steering current pulse is developed in plated wire 2 which causes the location 43 to become magnetized as a 1. In other words, the 1 data bit at location 32 has been logically transferred to location 43. The complement bit is transferred to location 44 as follows. The AND gate 82 is simultaneously energized by the signals T89 (FIG. 3j) and TRU-D (FIG. 3g). Hence, the AND gate 82 is condiitoned which in turn conditions the OR gate 78. The conditioning of the OR gate 78 causes the conductor 31 to be energized and the vectors at locations 44 to become biased. Since the fall time of the steering current pulse developed in plated wire 2 is terminated at the eighth clock pulse period (FIGS. 31' and 3e) and the bias pulse does not occur until after the ninth clock pulse (FIG. 3 the complement or 0 bit is transferred to location 44.

Information is transferred logically in a downward direction in the following manner. The information bit at location 43 is first transferred to location 55 and the complement of the information bit at location 44 is transferred to location 56. The vectors at the location 55 are first biased to the less than degree position. This accomplished by applying the signals T1-2 (FIG. BI) and TRR (FIG. 3k) to the AND gate 84 thereby conditioning the latter. The conditioning of the AND gate 84 causes the OR gate 87 to become conditioned which in turn causes the conductor 14 to be energized. Hence, the vectors at location 55 become biased. The signals T2-4 (FIG. 3d) and TRLR (FIG. 3a) are applied to the AND gate 79 thereby conditioning the latter. The output of the AND gate 79 is applied to the OR gate 77 so that the latter is conditioned and the conductor 30 is energized. Since location 43 is assumed to be a 1, a 1 bit is transferred to location '55. The complement bit is transferred to location 56 in the following manner. The signals T45 (FIG. 3m) and TRR (FIG. 3k) are simultaneously applied to the AND gate 83 thereby conditioning the latter. An output signal is thereby produced which is applied to the OR gate 88 so that the conductor 15 is energized. Accordingly, the magnetization vectors at location 56 become biased. Since the steering current which is developed in plated wire 2 (FIG. 3d) is terminated at the end of the clock time T4 whereas 1 l the bias signal (FIG. 3m) applied to conductor 15 does not terminate until the end of the fifth clock time, the complement bit at location 44 is transferred to location 56.

The 1 information bit at location 55 is next transferred to location 41 and the complement bit at location 55 is transferred to location 42 in the following logical manner. The vectors at location 41 are first biased by energizing conductor 39. This is accomplished by applying the signals T-1 (FIG. 3i) and TRUD (FIG. 3g) to the AND gate 61 thereby conditioning the latter. The conditioning of the AND gate 61 causes the OR gate 59 to be conditioned which in turn causes conductor 39 to be energized. Therefore, the vectors at location 41 become biased to the less than 90 degree position. The signals T1-3 (FIG. 3!) and the Read-Down signal (FIG. 3n) are simultaneously applied to the AND gate 85 so that the latter is conditioned. The conditioning of the AND gate 85 causes an output signal to be produced which is applied to the OR gate 87. This causes the OR gate 87 to be conditioned so that the conductor 14 is energized. Accordingly, a steering current pulse is developed in plated wires 2 and 7 which causes the 1 bit to be transferred from location 55 to location 41. The complement bit is transferred to location 42 as follows. The signals T3-4 (FIG. 3 and TRUD (FIG. 3g) are simultaneously applied to the AND gate 62. This causes the AND gate 62 to be conditioned and an output signal is produced thereby which is applied to the OR gate 60. This causes the OR gate 60 to be conditioned and the conductor 40 to be energized. Hence, the vectors at location 42 are biased to the less than 90 degree position. Since the steering current (FIG. 31) lasts until the end of the third clock pulse and the biasing signal applied to conductor 40 lasts until the end of the fourth clock pulse then the complement or 0 bit is transferred from location 56 to 42. The 1 data bit at location 41 and its complement at location 42 are next transferred, respectively, to locations 32 and 33. This is logically accomplished as follows. The vectors at location 32 are first biased by energizing conductor 30. The signals T56 (FIG. 3d) and TRUD (FIG. 3g) are simultaneously applied to the AND gate 81 soas to condition the latter. The conditioning of the AND gate 81 causes an output signal to be produced which is applied to the OR gate 77. Hence, conductor 30 is energized and the vectors at the location 32 are biased. The conductors 39 and 15 are then simultaneously energized. This is accomplished by applying the signals T68 (FIG. 31') and TRUD (FIG. 3g) to the AND gate 61 which causes the latter to be conditioned. The output of the AND gate 61 is applied to the OR gate 59 so that conductor 39 is energized. The signals T6-8 (FIG. 3m) and TRUD (FIG. 3g) are simultaneously applied to the AND gate 86 so that the latter is conditioned. The output of the AND gate 86 is applied to the OR gate 88 so that the conductor 15 is energized. Accordingly, a steering current pulse corresponding to (FIGS. 3m and 3i) is developed in plated wire 1 only, which causes the vectors at location 32 to be magnetized in the clockwise or 1 direction. The complement is transferred to location 33 by applying the signals T8-9 (FIG. 3 and TRUD (FIG. 3g) to the AND gate 82. The AND gate 82 is thereby conditioned which in turn conditions the OR gate 78. Hence, the conductor 31 is energized and the vectors at location 33 are biased. Since, the steering current which is developed in plated wire 1 is not terminated until the end of the eighth clock pulse and the biasing signal applied to conductor 31 does not terminate until the end of the ninth clock pulse, location 33 becomes magnetized in a counterclockwise or 0 direction.

In summary, this invention describes the operation whereby information is transferred from a first magnetizable wire to a second magnetizable wire in an upward or downward direction. This is accomplished by temporarily storing the information which is to be transferred to a third magnetizable wire which has a lower impedance than the first and second mentioned wires. The third magnetizable wire may be considered as a buffer or temporary store.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than specifically described.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. The combination comprising:

(a) a first data storage element of a first length;

(b) a second data storage element of said first length;

(c) a third data storage element of a second length wherein said first length is greater than said second length;

(d) means physically connecting one end of said first and second data storage elements to one end of said third data storage element and the other ends of said first, second and third elements being connected through ground potential;

(e) first means juxtaposed to said first and second data storage elements;

(f) second means juxtaposed to said third data storage element,

said first and second means coupling magnetic fields to said first, second and third data storage elements when energized for transferring information from said first to said second data storage element via said third data storage element.

2. The combination in accordance with claim 1 wherein information is transferred from said first data storage element to said second data storage element via said third data storage element by selectively energizing said first and second means.

3. The combination in accordance with claim 1 wherein the impedance of said first and second data storage element is greater than the impedance of said third data storage element.

4. The combination in accordance with claim 1 wherein said first and second data storage elements are magnetizable along a first portion of its length and a second portion being non-magnetizable.

5. The combination in accordance with claim 4 wherein said magnetizable portion of said first and second data storage elements comprises a substrate having a magnetic coating with the property of uniaxial anisotropy.

6. The combination in accordance with claim 4 wherein said first means which are juxtaposed to said first and second data storage elements are oriented along said magnetizable first portion of said first data storage element and along said second non-magnetizable portion of said second data storage position.

7. The combination in accordance with claim 6 wherein said first means comprises at least one conductor oriented substantially orthogonal to said first and second data storage along their magnetizable portions, at least two conductors for temporary data storage oriented substantially orthogonal to said first magnetizable portion of said first data storage element and to said second nonmagnetizable portion of said second data storage position.

8. The combination in accordance with claim 1 including a fourth data storage element of said first length and a fifth data storage element of said second length, said fifth data storage element being physically connected to the remaining end of said second data storage element and to one end of said fourth data storage element.

9. The combination in accordance with claim 8 wherein said fourth data storage element is magnetizable along a first portion of its length and a second portion being non-magnetizable.

10. The combination in accordance with claim 8 wherein a third means which is adapted to be connected to an energizing means is juxtaposed to said first, second, fourth and fifth data storage means.

11. The combination in accordance with claim 10 wherein said third means juxtaposed to said second and fourth data storage elements are oriented along said magnetizable portion of said second data storage element and along said non-magnetizable portion of said first and fourth data storage element.

12. The combination in accordance with claim 10 wherein said third means comprises at least two conductors oriented substantially orthogonal to said second data storage element along its magnetizable portion and substantially orthogonal to said first and fourth data storage element along its non-magnetizable portion, and at least two conductors oriented substantially orthogonal to said fifth data storage element.

13. The combination in accordance with claim 9 wherein information is transferred from said second data storage element to said first data storage element via said third data storage element by selectively energizing said second and first juxtaposed means.

14. The combination in accordance with claim 10 wherein information is transferred from said first data storage element to said fourth data storage element and in the alternative, from said fourth data storage element to said first data storage element via said third and fifth data storage element by selectively energizing said first and third coupling means.

15. The combination comprising:

(a) a first data storage element of a first length which is magnetizable along a first portion of its length, a second portion of its length being non-magnetizable;

(b) a second data storage element of said first length which is magnetizable along a first portion of its length, a second portion of its length being nonmagnetizable;

(c) a third data storage element of a second length which is magnetizable physically joined by connector means to one end of said first and second elements,

the other end of said first, second and third data storage elements being at ground potential;

((1) at least one conductor means juxtaposed to said magnetizable portion of said first and second data storage elements;

(e) at least four conductor means juxtapoesd to said first magnetizable portion of said first data storage element and to said non-magnetizable portion of said second data storage element, the intersection of two of said conductor means with said first data storage element being permanently magnetized as a binary zero and one, respectively, said four conductor means adapted to be connected to energizing means;

(f) at least four conductor means juxtaposed to said first magnetizable portion of said second data storage element and to said non-magnetizable portion of said first data storage element, the intersection of two of said coupling means with said second data storage element being permanently magnetized as a binary zero and one, respectively, said four conductor means adapted to be connected to energizing means;

(g) at least four conductor means which are adapted to be connected to energizing means juxtaposed to said third data storage element, the intersection of two of said coupling means with said third data storage position being permanently magnetized as a binary zero and one, respectively.

16. The combination in accordance with claim 1 wherein said second means comprises at least two conductors oriented substantially orthogonal to said third data storage element.

References Cited UNITED STATES PATENTS 3,223,986 l2/1965 Clark 340l74 3,377,581 4/1968 Boles et al 340l74 BERNARD KONICK, Primary Examiner STEVEN B. POKOTILOW, Assistant Examiner 

